Nehalem and It’s Successors

Intel

Nehalem, Intel new archi­tec­ture is not yet offi­cially launched,? But we got inform­a­tion about it’s suc­cessors, on which? intel is work­ing on. The new CPU there­fore fol­low the pat­tern of devel­op­ment “Tick-Tock”, i.e; a new archi­tec­ture every two years (Tock), fol­lowed by a die shrink (Tick). In exclus­iv­ity, here are the code names of future gen­er­a­tions of pro­cessors, and until 2012

Intel TickTock Development Model

  • West Mere (Tick, 2009, 32 nm)
  • Sandy Bridge (Tock, 2010, 32 nm)
  • IVY Bridge (Tick, 2011, 22 nm)
  • Haswell (Tock, 2012, 22 nm)

Cur­rently Penryn (Tick, 2008, 45nm) are avail­able in mar­ket which are engraved in 45nm die. At the end of the 2008 the new gen­er­a­tion Nehalem(Tock, 2008, 45nm) engraved in 45nm die. Then the Westmere(Tick, 2009, 32nm) Neh­lam archi­tec­ture engraved in 32nm die. Then comes Sandybridge(Tock, 2010, 32nm) engraved in 32nm die. And it goes to Ivy Bridge(Tick, 2011, 22nm) then to Haswell(Tock,2012,22nm) engraved in 22nm die.

First We talk about Nehalem, Which is suc­cessor of core2 archi­tec­ture mainly comes with more num­ber of cores(upto 8), cache, Integ­rated memory con­trol­ler. Nehalem will have 32 KB L1 cache Data, 256 KB L2 cache with very low latency by heart and a L3 cache of vary­ing size (up to 8 MB on the Desktop ver­sions). Nehalem will also have the Hyper­thread­ing, which allows the exe­cu­tion threads 2 by heart. The effect­ive­ness of this tech­no­logy on this type of archi­tec­ture at short pipeline remains questionable.

Sandy Bridge, the next Intel archi­tec­ture. So far about this to the fact that they are man­u­fac­tured in 32 nm would and would likely 2010. It comes with AVX, was not neces­sar­ily dir­ectly with Sandy Bridge in con­nec­tion. Now, how­ever: Sandy Bridge is the first Intel CPU, the AVX, the SSE suc­cessor. Sup­posedly AVX sim­il­ar take as SSE 1999 to the Pen­ti­um pro­cessors. The fol­low­ing lists the grossest film improvements.

AVX with SandybridgeAVX with Sandybridge

  • The exten­sion of the cur­rent SSE registers 128 to 256 bits, while remain­ing com­pat­ible with 128-bit SSE instructions.
  • The rearrange­ment advanced data: a single oper­a­tion can sim­ul­tan­eously handle 8 data bits 32
  • The pos­sib­il­ity to use three or four operands

For Sandy­bridge, each core will be giv­en on a 512 KiB large L2 cache, while a 16 MB large L3 cache access­ible to all cores.

Haswell, Planned for 2012 or earli­er, the fam­ily Haswell suc­cessor archi­tec­ture of Sandy Bridge. engraved to 22 nm, they should include 8‑core default, a whole new archi­tec­ture caches, “revolu­tion­ary” energy sav­ing and the pos­sib­il­ity of board cop­ro­cessors vec­tor pro­cessing in a single pack­age. New instruc­tion set, FMA (Fused Mul­tiply-Add), which allows sim­ul­tan­eous oper­a­tion of mul­ti­plic­a­tion and addi­tion via the same instruc­tion, should be implemented.