Nehalem and It’s Successors

Intel

Nehalem, Intel new archi­tec­ture is not yet offi­cial­ly launched,? But we got infor­ma­tion about it’s suc­ces­sors, on which? intel is work­ing on. The new CPU there­fore fol­low the pat­tern of devel­op­ment “Tick-Tock”, i.e; a new archi­tec­ture every two years (Tock), fol­lowed by a die shrink (Tick). In exclu­siv­i­ty, here are the code names of future gen­er­a­tions of proces­sors, and until 2012

Intel TickTock Development Model

  • West Mere (Tick, 2009, 32 nm)
  • Sandy Bridge (Tock, 2010, 32 nm)
  • IVY Bridge (Tick, 2011, 22 nm)
  • Haswell (Tock, 2012, 22 nm)

Cur­rent­ly Pen­ryn (Tick, 2008, 45nm) are avail­able in mar­ket which are engraved in 45nm die. At the end of the 2008 the new gen­er­a­tion Nehalem(Tock, 2008, 45nm) engraved in 45nm die. Then the Westmere(Tick, 2009, 32nm) Nehlam archi­tec­ture engraved in 32nm die. Then comes Sandybridge(Tock, 2010, 32nm) engraved in 32nm die. And it goes to Ivy Bridge(Tick, 2011, 22nm) then to Haswell(Tock,2012,22nm) engraved in 22nm die.

First We talk about Nehalem, Which is suc­ces­sor of core2 archi­tec­ture main­ly comes with more num­ber of cores(upto 8), cache, Inte­grat­ed mem­o­ry con­troller. Nehalem will have 32 KB L1 cache Data, 256 KB L2 cache with very low laten­cy by heart and a L3 cache of vary­ing size (up to 8 MB on the Desk­top ver­sions). Nehalem will also have the Hyper­thread­ing, which allows the exe­cu­tion threads 2 by heart. The effec­tive­ness of this tech­nol­o­gy on this type of archi­tec­ture at short pipeline remains ques­tion­able.

Sandy Bridge, the next Intel archi­tec­ture. So far about this to the fact that they are man­u­fac­tured in 32 nm would and would like­ly 2010. It comes with AVX, was not nec­es­sar­i­ly direct­ly with Sandy Bridge in con­nec­tion. Now, how­ev­er: Sandy Bridge is the first Intel CPU, the AVX, the SSE suc­ces­sor. Sup­pos­ed­ly AVX sim­i­lar take as SSE 1999 to the Pen­tium proces­sors. The fol­low­ing lists the gross­est film improve­ments.

AVX with SandybridgeAVX with Sandybridge

  • The exten­sion of the cur­rent SSE reg­is­ters 128 to 256 bits, while remain­ing com­pat­i­ble with 128-bit SSE instruc­tions.
  • The rearrange­ment advanced data: a sin­gle oper­a­tion can simul­ta­ne­ous­ly han­dle 8 data bits 32
  • The pos­si­bil­i­ty to use three or four operands

For Sandy­bridge, each core will be giv­en on a 512 KiB large L2 cache, while a 16 MB large L3 cache acces­si­ble to all cores.

Haswell, Planned for 2012 or ear­li­er, the fam­i­ly Haswell suc­ces­sor archi­tec­ture of Sandy Bridge. engraved to 22 nm, they should include 8‑core default, a whole new archi­tec­ture caches, “rev­o­lu­tion­ary” ener­gy sav­ing and the pos­si­bil­i­ty of board coproces­sors vec­tor pro­cess­ing in a sin­gle pack­age. New instruc­tion set, FMA (Fused Mul­ti­ply-Add), which allows simul­ta­ne­ous oper­a­tion of mul­ti­pli­ca­tion and addi­tion via the same instruc­tion, should be imple­ment­ed.